The acronym PCI stands for Peripheral Component Interconnect, which aptly describes what it does. PCI was designed to satisfy the requirement for a standard interface for connecting peripherals to a PC, capable of sustaining the high data transfer rates needed by modern graphics controllers, storage media, network interface cards and other devices.
Earlier bus designs were all lacking in one respect or another. The IBM PC-AT standard ISA (Industry Standard Architecture) bus, for example, can manage a data transfer rate of 8MB/sec at best. In practice, the throughput that can be sustained is much less than that. Other factors, like the 16-bit data bandwidth and 24 bit wide address bus - which restricts memory mapped peripherals to the first 16MB of memory address space - made the ISA bus seem increasingly outmoded .
More recent designs such as IBM's MCA (Micro Channel Architecture) and the EISA (Extended ISA) bus, though having higher bandwidth (32 bits) and providing better support for bus mastering and direct memory access (DMA), were not enough of an improvement over ISA to offer a long term solution. New, faster versions of both MCA and EISA were proposed, but were received without enthusiasm. Neither promised to be an inexpensive solution, and cost has always been an important factor in the competitive PC market.
VL BUS
One attempt to improve bus performance inexpensively was the VL-Bus. Prior to this, some PC vendors had started providing proprietary local bus interfaces enabling graphics boards to be connected directly to the 486 processor bus. These systems had one major failing: since the interfaces were proprietary, support for them by third-party peripheral vendors was limited, so there was little chance that a user would ever be able to purchase a compatible graphics card as an upgrade.
VESA's intervention gave manufacturers a standard to work to. The standard was based on existing chip sets. This had the advantages of low cost, and of enabling the technology to be got to market quickly. The disadvantage was the rather crude implementation. The VL-Bus was a success in its day because it met a need, but it never looked like a long term solution.
Some of the parties involved in the design of the VL-Bus standard felt that a solution based on existing bus technologies had too many design compromises to be worth considering. This group, led by Intel, split off to form the PCI Special Interest Group with the aim of producing a new bus specification from scratch.
Although PCI has been described as a local bus, in fact it is nothing of the sort. The term 'local bus' means that the address, data and control signals are directly connected - in other words, 'local' - to the processor. The VL-Bus is a true local bus, since devices are connected to the CPU via nothing more than some electrical buffering. This is one of the reasons for its simplicity, but it is also the reason for many of its limitations.
One problem is that a local bus is by definition synchronous. The bus speed is the same as the external processor clock speed. Expansion card vendors therefore have the difficulty of ensuring that their products will run at a range of speeds. The upper limit of the range cannot be defined, and is liable to increase as new processors are introduced. This is a recipe for compatibility problems. Such problems have been experienced by users of VL-Bus systems using the AMD 80MHz processors, which have a 40MHz bus clock.
The second problem with a true local bus is that the electrical load (and consequently the number of expansion slots) that can be driven by the bus decreases as the clock speed increases. This creates the situation where typically three slots can be provided at 33MHz, but only two at 40MHz and just one at 50MHz. This is particularly awkward given that most motherboards are designed to work at a range of clock speeds and usually come with three slots. Many manufacturers simply ignored the problem.
PCI DESIGN
PCI's designers decided to avoid these difficulties altogether by making PCI an asynchronous bus. The top speed for most PCI cards is 33MHz. The PCI 2.1 specification made provision for a doubling of the speed to 66MHz, but support for this higher speed was optional.
At 33MHz, with a 32-bit data bus, the theoretical maximum data transfer rate of the PCI bus is 132MB/sec. At 66MHz, with a 64-bit data path, the top speed would be 528MB/sec.
The PCI bus can run at lower speeds. In a system clocked at 25MHz, for example, the bus could also run at this speed. This was an important consideration at the time PCI was being developed.
Peripherals must be designed to work over the entire range of permitted speeds. In the original PCI specification the lower limit to the speed range was given as 16MHz; in PCI revision 2.0 this was reduced to 0MHz. This supports 'green' power saving modes by allowing the system to run at reduced speed for lower power consumption, or to be put into 'suspend' mode (0MHz), without any bus status information being lost.
The number of devices on a PCI bus depends on the load. In practice this means three or four slots, plus an on-board disk controller and a secondary bus. Up to 256 PCI busses can be linked together, though, to provide extra slots, so this is not really a limitation.
INTERRUPT HANDLING
The concept of 16 discrete IRQ lines, each uniquely assigned to a device, is peculiar to the ISA bus and its derivatives. The CPU sees only a single interrupt signal, obtains an interrupt vector address and then processes the interrupt routine at that address. The use of 16 lines was the method chosen by the designers of the original IBM PC to tell the interrupt controller which address to supply.
Each PCI slot has four interrupt lines connected to it, designated INTA# to INTD#. The first (or only) interrupt-using function on a PCI board must be connected to INTA#. The other three lines allow up to four functions to be combined on one board using INTA# - INTD# in that order.
The PCI interrupt lines and the output from the ISA interrupt controller are combined in a programmable interrupt router, which generates the single interrupt signal for the CPU. How they are combined is not defined by the PCI specification. PCI interrupts are edge-triggered and therefore shareable, so some of them may be connected together.
The IBM PC architecture expects particular devices to use particular IRQs (e.g. the primary disk controller must use IRQ14). Furthermore, because ISA interrupt lines cannot be shared, PC interrupt routines expect that when they are called, they are servicing their specific device and no other.
This means that in a PC, the INTx# lines in each PCI slot - or those that are being used - must each be mapped to a separate IRQ which the operating system or driver software will expect the device in that slot to use. This is usually done using the BIOS Setup utility. Some early PCI systems which did not have this facility required an ISA 'paddle-board' to be used with add-ins like caching disk controllers to ensure they were connected to the appropriate IRQ.
Integrated (on-board) devices are hard-configured to use the appropriate interrupts. Were it not for the fact that specific devices must use specific IRQs, PCI configuration would be completely automatic as the interrupt level could be assigned by the system at start-up.
The PCI bus was an expansion bus designed to meet the requirements of PC users now and for the foreseeable future,. With its high speed, 64-bit data bandwidth and wholehearted support for bus mastering and burst mode data transfers, its maximum throughput is unlikely to become a bottleneck for some time. And its processor independence will be a valuable asset as our PCs move further away from the limitations of the '80s Intel x86 architecture.
From a support point of view, PCI's plug-and-play ambitions are welcome. We are never likely to see completely automatic configuration, nor get away from such restrictions as 16 interrupt request lines, while we continue to demand PC compatibility. But PCI, which inherits none of these limitations, is a step in the right direction.
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